Lead Digital Verification Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This is an opportunity to join a dynamic team of experienced engineers developing high-performance physical IP for industry-standard protocols.

The successful candidate will be a highly motivated self-starter who is able to work independently to complete assigned tasks and can also contribute to project leadership.

The candidate will contribute to all aspects of digital verification including flow development, test plan development and execution, functional coverage closure, and code coverage closure.

It is expected that the candidate will be able to work as part of a small and focused team of engineers and will be able to collaborate successfully as needed with design architects and project management.

Candidate should be willing to work full time in the Montreal, QC, Canada office and be willing to travel as required by job function (expectation is 5% travel or less).

The successful candidate will have a thorough understanding of all aspects of modern digital verification flows, including but not limited to the following:

+ Verification environment architecture and methodologies

Metric-driven verification

Universal Verification Methodologies (UVM)

Constrained random testing

Test plan development

Functional coverage

Code coverage

System Verilog Assertions (SVAs)

Formal Verification

Should be able to contribute to test plan development, coverage closure, and regression failure analysis at both block and subsystem level.

Candidate should be have experience with SystemVerilog and should have a working knowledge of at least one EDA verification planning tool.

Direct experience with at least one of the following protocols is strongly preferred:

PCIExpress Gen1/2/3/4/5/6

Gigabit Ethernet

AMBA/APB/AXI/AHB

USB

Candidate should be capable of leveraging scripting languages (Tcl, Perl, Python, Awk, Make, etc) to assist with automation and efficiency improvements in the verification flow.

Candidate is also expected to be able to clearly communicate with design and architecture resources to accurately describe verification failures and contribute to issue resolution.

Excellent logic debug skills are a must, and the ability to operate independently and as part of a dedicated and focused team is also critical.

Demonstrated ability to lead small verification teams is strongly preferred.

We're doing work that matters. Help us solve what others can't.

We welcome applications from candidates with disabilities and in equity seeking groups. If you have accessibility needs during the application and interview process, we encourage you to make your needs known.

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Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For.

Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.