Physical Design Engineer

This role is for one of the Weekday's clients Salary range: Rs 2500000 - Rs 7500000 (ie INR 25-75 LPA)

Experience: 7+ yrs Location: Bengaluru Job Type: full-time

We are seeking an experienced Physical Design Engineer to join our semiconductor engineering team and contribute to the successful implementation of complex ASIC and SoC designs. The ideal candidate will have 7?12 years of hands-on experience in end-to-end ASIC physical design, with strong expertise in Cadence Innovus, TSMC advanced process technologies, and the complete physical implementation flow from synthesis handoff through tape-out. This role requires a strong understanding of timing, power, area, and signal integrity optimization, along with the ability to deliver high-quality silicon designs while collaborating with cross-functional engineering teams. The position offers an opportunity to work on advanced semiconductor technologies and high-performance chip development projects. Requirements Key Responsibilities

• Execute the complete ASIC physical design flow from synthesis handoff to tape-out for complex SoC and ASIC designs.
• Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical optimization using Cadence Innovus.
• Drive timing closure while optimizing power, performance, and area (PPA) across all stages of physical implementation.
• Perform signal integrity analysis, congestion optimization, and design rule compliance to ensure robust chip implementation.
• Work with TSMC advanced technology nodes and implement designs according to process-specific requirements and best practices.
• Collaborate with RTL, Design, DFT, STA, and Verification teams to resolve implementation challenges and achieve project milestones.
• Analyze and resolve setup and hold timing violations, congestion issues, and physical design bottlenecks.
• Support engineering change orders (ECOs) and implement design modifications during the physical design cycle.
• Perform quality checks including DRC, LVS, and physical verification to ensure tape-out readiness.
• Prepare technical documentation, implementation reports, and design reviews while contributing to continuous process improvements.

• 7?12 years of hands-on experience in ASIC physical design and implementation.
• Strong expertise in Cadence Innovus across the complete physical design flow.
• Proven experience working with TSMC advanced technology nodes and complex SoC designs.
• Solid understanding of floorplanning, power planning, placement, CTS, routing, timing closure, and physical verification.
• Strong knowledge of timing analysis, signal integrity, power optimization, and PPA improvement techniques.
• Experience resolving timing, congestion, and implementation challenges for high-performance semiconductor designs.
• Familiarity with DRC, LVS, ECO implementation, and tape-out methodologies.
• Strong analytical, debugging, and problem-solving skills with attention to detail.
• Excellent communication and collaboration skills, with the ability to work effectively across multidisciplinary engineering teams.
• Self-motivated, quality-focused, and capable of delivering high-quality physical design solutions within project timelines.