SoC Design Engineer

Syntiant Corp., a leader in the high-growth AI software and semiconductor solutions space, has entered into an agreement to acquire a large, multi-national sensor business with global revenues in excess of $250 million per year, and is looking for an experienced and talented SoC Design Engineer .

The SoC Design Engineer will be responsible for developing Syntiant's next generation Neural Decision Processor SoCs. The ideal candidate will be a self-starter who can execute all design cycle tasks from architecture to tapeout as well as silicon bring-up and validation while working with cross-disciplinary teams (Design, Firmware, Product, OPS & Field Engineering).

Specific Duties and Responsibilities:

• Microarchitecture and implementation of SoC design blocks
• Integrate and verify design blocks at chip level
• Quality checks of the implemented RTL with LINT, CDC and DFT rules with clear documentation of exceptions and waivers
• Synthesis, constraints and timing closure for the SoC
• Logic Equivalence Check (LEC) for SoC design blocks and for the full SoC
• Implement low power modes for the SoC using UPF
• Implement Design-for-Test (DFT) features in the SoC
• Participate in silicon bring-up, validation and characterization
• Provide quality documentation of the implementation and other deliverables with systematic reviews.
• Work with OPS team to resolve volume manufacturing issues
• Work with cross functional teams to debug and resolve platform and customer issues

Requirements

• Advanced degree in electrical engineering or computer engineering
• Track record of 'first-pass success' in ASIC development cycles
• 6+ years of experience with SoC development using SystemVeilog/Systemc
• Expertise in SoC and Subsystem design of ARM based SoCs
• Deep understanding of Synthesis, constraint development and timing closure
• Deep understanding of design quality checks (Lint, CDC, DFT rules)
• Experience with Low Power Design using UPF
• Experience with scripting languages, e.g. Python
• Experience with High Level Synthesis (HLS) using SystemC is a big plus
• Experience with silicon bring up and debug as well as developing chip demo
• Experience with SoC performance analysis is a plus
• Knowledge of ARM architecture and AMBA bus standards like AXI, AHB & APB
• Knowledge of Design for Test (DFT) features and implementation is a plus
• Knowledge of SoC power estimation flow is a plus