Senior ASIC Design Engineer - PCIE

The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior ASIC Design Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge.

Work hard. Have Fun. Make history.

Key job responsibilities

In this role, you work in a team developing SoCs to be deployed in a range of Amazon devices. You will be responsible for design of RTL components and integrate 3rd party IPs as well as internal IP's into Amazon SoC. This role requires in depth knowledge in one or more of these areas: Fabric, memory controller, CPU, Caches, Coherence, MMU, Security, High Speed Interfaces/Protocols to integrate third party IPs and commonly used SoC blocks (controllers, memories, I/Os) into the SOC. You will work closely with System Architects, SoC architects, IP developers and physical design teams to develop SoCs that meets the power, performance and area goals for Amazon devices. You will help define the processes, methods and tools for design and implementation of large complex SoCs.

Work with Chip Architects to understand architecture and high-level product requirements.

Convert Chip Spec into RTL using internal IPs and external IPs.

Review Architecture and Design of custom IPs for integration into SOC?s.

Develop and implement methodologies for I/O, DFT, Debug, Clocking and Power Management.

Design & Develop RTL for Interfaces, Power Management, Clocking, Test & Debug.

Provide technical leadership through lead by example, mentorship and strong team work.

Basic Qualifications

BS degree or higher in EE or CE or CS 10+ years or more of practical semiconductor design experience including full-chip and subsystem integration

Experience in micro-architecture definition from architecture guideline and model analysis

Strong experience in PCIE

Experience in RTL coding (Verilog/System Verilog) and debug, as well as performance/power/area analysis and trade-offs

Experience in closing full-chip and subsystem timing working with synthesis and static timing analysis teams

Successful tape outs of complex, high-volume SoCs in advanced design nodes

Experience with DFT tools for scan and BIST insertion Excellent verbal and written communication skills, collaboration and teamwork skills as well as ability to contribute to diverse and inclusive teams.

Preferred Qualifications

In-depth knowledge of in one or more areas such as CPU, DSP, or programmable accelerators

Design experience in Datapath, flow control, Arbitration, FIFO, DMA , IOMMU, SOC bus architectures, Arteris NOC interconnect, ARM?s AXI/AHB bus architecture & Protocols, Serial interfaces such as PCIe, QSPI, I2C,UART, EMMC, USB. LPDDR controller & Phy IP integration, embedded memory (SRAM, OTP etc;)

Other IP integration such as ADC, PLL, DLL, PVT sensors & Debug(Coresight) SOC bring-up and post silicon validation experience

Experience with RTL power analysis

Experience with gate level testing and multi clock design practices

Experience working with software teams to tightly define the HW/SW interface including control/status registers, and error handling

Experience working closely with physical design teams to develop highly optimized ASICs with excellent power, performance and area

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