Principal Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.

Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.

Cadence?s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.

The unique ?One Cadence ? One Team? culture promotes collaboration within and across teams to ensure customer success

Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests

You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other?every day.

Job responsibilities:

BE/BTECH/ME/MTECH Or Equivalent Degree

RESPONSIBILITIES:

Develop test plans, tests , and verification infrastructure for complex IP?s/sub-system/SOC?s.

Create verification environment using UVM methodology.

Create reusable bus functional models, monitors, checkers, and scoreboards.

Drive functional coverage driven verification closure.

Work with architects, designers and DFT teams.

SKILL SETS:

BTech/ MTech with 10-14 years of experience.

IP/Sub-system/SOC level verification experience.

Expert in developing test bench/test case using System Verilog & UVM.

Experience in leading verification closure of complex IP/SOC for at least one project.

Experience with code coverage, functional coverage & assertions is desired.

Experience in at least one of the following areas:

CPU verification

Memory controller verification

DDR Protocol - DDR4, DDR5, LPDDR4 and LPDDR5

USB 2 and USB 3 protocol

PCIE

+ Bus protocols (AXI/AHB/APB)

Exposure to industry standard verification tools for simulation and debug

Good debugging and problem-solving skills.

Good communication skills

We're doing work that matters. Help us solve what others can't.

Additional Jobs (https://cadence.wd1.myworkdayjobs.com/addl\_jobs)

Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For.

Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.