DFT Engineer

This role is for one of the Weekday's clients Min Experience: 3+ years Location: Hyderabad JobType: full-time

We are looking for a skilled and detail-oriented DFT Engineer to join our semiconductor design team in Hyderabad. This role is ideal for professionals with hands-on experience in Design for Test (DFT) methodologies and a strong background in implementing robust test solutions for complex ASIC and SoC designs. The ideal candidate must have deep expertise in MBIST (Memory Built-In Self-Test), along with practical experience in Scan Insertion, DFT implementation, and test architecture. As a DFT Engineer, you will work closely with design, verification, physical design, and test engineering teams to ensure high manufacturing quality, test coverage, and silicon reliability. You will be responsible for implementing and validating DFT features while optimizing designs for efficient production testing. Requirements Key Responsibilities

• Design, implement, and validate DFT solutions for ASIC and SoC designs.
• Develop and integrate MBIST architectures for embedded memories.
• Perform Scan Insertion, scan chain verification, and scan optimization.
• Generate and validate ATPG patterns to achieve high fault coverage.
• Implement and debug JTAG and boundary scan functionality.
• Define and enhance DFT architecture to meet testability and quality requirements.
• Work closely with RTL, verification, and physical design teams to ensure smooth DFT integration.
• Analyze test coverage reports and identify opportunities to improve manufacturing test quality.
• Debug DFT-related issues during simulation, synthesis, and silicon bring-up.
• Ensure compliance with industry-standard DFT methodologies and best practices.
• Support post-silicon validation and production test activities whenever required.
• Prepare technical documentation and collaborate with cross-functional teams throughout the product development lifecycle.

• Strong expertise in Design for Test (DFT) methodologies.
• Hands-on experience with MBIST implementation and validation.
• Solid experience in Scan Insertion and scan chain verification.
• Good understanding of ATPG concepts, fault models, and coverage analysis.
• Experience with JTAG and boundary scan implementation.
• Strong knowledge of DFT architecture for ASIC/SoC designs.
• Familiarity with digital design fundamentals and RTL concepts.
• Strong debugging and problem-solving abilities.

• Experience with Tessent or Synopsys DFT tools.
• Knowledge of Verilog and SystemVerilog.
• Understanding of synthesis and STA concepts.
• Familiarity with semiconductor design and manufacturing test flows.
• Exposure to scripting languages such as Tcl, Perl, or Python is an advantage.
• Excellent communication and collaboration skills.

• Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Computer Engineering, or a related field.
• 3?5 years of relevant experience in DFT engineering within semiconductor or VLSI product development.
• Proven experience delivering DFT solutions for complex ASIC or SoC designs.