Design Verification Lead

Creates quality emulation collaterals using UVM System Verilog/SystemC and integrates it with the emulation/FPGA model. Tests and debugs the emulation/FPGA model and collaterals for validation readiness. Defines and develops new capabilities & HW/SW tools to enable acceleration of RTL and improve emulation/FPGA model usability for pre-silicon and post-silicon functional and performance validation as well as SW development/validation. Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform. Interfaces with and provides guidance to presilicon Validation teams for optimizing pre-silicon validation environments, test suites and methodologies for emulation efficiency. Develops and applies automation aids, flows and scripts in support of emulation ease of use and improvement of equipment utilization.

Job Experience:

Technical experience in verification of RTL-based digital systems with very good understating of various system level flows

Experience leading development of verification architecture based on evolving requirement from IP/SOC customers

Experience with RTL design, Verilog and simulation, debug tools such as Verdi, System Verilog/SystemC based verification techniques.

Experience in debugging and isolation techniques including writing checkers, monitors, assertions and necessary DPI interfaces for co-emulation environments

Experience in SW Programming/scripting and debug such as C, C++, Perl, Python

Work experience creating a self-checking emulation/simulation test bench

Highly proficient in UVM techniques for verification

Hands-on experience of emulation and simulation BFM based verification

Good understanding of architectural design documents(micro-architecture documents, integration documents)

Preferably good understanding of emulation/simulation platform with major vendors (Synopsys, cadence )

Protocol knowledge : PCIE, CXL, UCIe, CHI, DDR

Good understanding of CPU architecture (Intel/AMD/Arm/GPU)

Highly proficient with coherent, non-coherent and concurrent traffic validation

Experience with emulation based systems such as Synopsys ZeBu, Cadence Palladium or Mentor Graphic Veloce

Experience in building emulation based models for large scale designs is a plus

Job Responsibilities:

Work closely with peers in architecture, design and verification teams

Should be able to review the IP teams requirements, come up with verification plan, test plan, micro-arch, identify scenarios and design intent and develop verification strategies which can ensure defect free IP's

Maintain generic emulation based verification environment and regression setups for various IP's

Leads activities driving the development of various stimulus to support the emulation based verification of various IP's

Develop and maintain UVM environments for IP interfaces

Work in cross-functional teams to deliver bug free features in a timely manner

Qualifications

Qualifications

This position requires meeting the below minimum qualifications to be initially considered. Preferred qualifications are in addition to the minimum requirements and are considered a major plus.

Minimum Qualifications:

Must have a Bachelor's degree with 15+ year experience or Master's degree in Electronics and Computer Engineering with relevant experience of at least 10+ years

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations.

DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams.

As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.

Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel's offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Job posting details (such as work model, location or time type) are subject to change.